1. Technical Field
The present invention relates to field effect transistors (FETs), and more specifically, to staircase silicide FETs.
2. Related Art
In a typical field effect transistor (FET), there is a trade-off balance between (a) operation control and (b) resistance. More specifically, to have a better control of the threshold voltage Vt of the FET (so-called short channel effect), the FET's source/drain (S/D) extension regions which are in direct physical contact with the FET's channel region are formed as thin as possible. However, the thinner the S/D extension regions, the higher the resistances of these S/D extension regions, which is undesirable.
Therefore, there is a need for an FET (and a method for forming the same) which has a better trade-off balance between operation control and resistance than that of the prior art.